Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis

Kaijie Wu, Ramesh Karri. Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. In Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA. pages 902-911, IEEE Computer Society, 2003. [doi]

Abstract

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