Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis - researchr publication related

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Kaijie Wu, Ramesh Karri. Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. In Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA. pages 902-911, IEEE Computer Society, 2003. [doi]

The following publications are possibly variants of this publication:

Fault secure datapath synthesis using hybrid time and hardware redundancyKaijie Wu, Ramesh Karri. tcad, 23(10):1476-1485, 2004. [doi]

Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesisRamesh Karri, Balakrishnan Iyer, Israel Koren. tcad, 21(8):877-888, 2002. [doi]

Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection techniqueKaijie Wu, Ramesh Karri. itc 2001: 221-229

Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetectionKaijie Wu, Ramesh Karri. tcad, 21(9):1077-1087, 2002. [doi]

Phantom redundancy: a high-level synthesis approach for manufacturabilityBalakrishnan Iyer, Ramesh Karri, Israel Koren. iccad 1995: 658-661 [doi]

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