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FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations

Wei Wu, Yi Shan, Xiaoming Chen, Yu Wang, Huazhong Yang. FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations. In Andreas Koch, Ram Krishnamurthy, John McAllister, Roger Woods, Tarek A. El-Ghazawi, editors, Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings. Volume 6578 of Lecture Notes in Computer Science, pages 302-315, Springer, 2011. [doi]

Authors

Wei Wu

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Yi Shan

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Xiaoming Chen

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Yu Wang

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Huazhong Yang

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