Wei Wu, Yi Shan, Xiaoming Chen, Yu Wang, Huazhong Yang. FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations. In Andreas Koch, Ram Krishnamurthy, John McAllister, Roger Woods, Tarek A. El-Ghazawi, editors, Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings. Volume 6578 of Lecture Notes in Computer Science, pages 302-315, Springer, 2011. [doi]
@inproceedings{WuSCWY11,
title = {FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations},
author = {Wei Wu and Yi Shan and Xiaoming Chen and Yu Wang and Huazhong Yang},
year = {2011},
doi = {10.1007/978-3-642-19475-7_33},
url = {http://dx.doi.org/10.1007/978-3-642-19475-7_33},
researchr = {https://researchr.org/publication/WuSCWY11},
cites = {0},
citedby = {0},
pages = {302-315},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings},
editor = {Andreas Koch and Ram Krishnamurthy and John McAllister and Roger Woods and Tarek A. El-Ghazawi},
volume = {6578},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-642-19474-0},
}