A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS

Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013. pages 2239-2242, IEEE, 2013. [doi]

@inproceedings{WuZDCCSUM13,
  title = {A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS},
  author = {Wen-Lan Wu and Yan Zhu and Li Ding and Chi-Hang Chan and U. Fat Chio and Sai-Weng Sin and Seng-Pan U. and Rui Paulo Martins},
  year = {2013},
  doi = {10.1109/ISCAS.2013.6572322},
  url = {http://dx.doi.org/10.1109/ISCAS.2013.6572322},
  researchr = {https://researchr.org/publication/WuZDCCSUM13},
  cites = {0},
  citedby = {0},
  pages = {2239-2242},
  booktitle = {2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013},
  publisher = {IEEE},
  isbn = {978-1-4673-5760-9},
}