Yang Xia, Pranav Ashar. Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. In 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India. pages 449, IEEE Computer Society, 2000. [doi]
@inproceedings{XiaA00, title = {Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture}, author = {Yang Xia and Pranav Ashar}, year = {2000}, url = {http://csdl.computer.org/comp/proceedings/vlsid/2000/0487/00/04870449abs.htm}, tags = {rule-based, architecture}, researchr = {https://researchr.org/publication/XiaA00}, cites = {0}, citedby = {0}, pages = {449}, booktitle = {13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India}, publisher = {IEEE Computer Society}, }