Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization - researchr publication authors

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Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu 0001, Shouyi Yin. Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. In Vivek De, editor, Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024. ACM, 2024. [doi]

This author has not been identified. Look up 'Xujiang Xiang' in GoogleThis author has not been identified. Look up 'Zhiheng Yue' in GoogleThis author has not been identified. Look up 'Yuxuan Li' in GoogleThis author has not been identified. Look up 'Liuxin Lv' in GoogleThis author has not been identified. Look up 'Shaojun Wei' in GoogleThis author has not been identified. Look up 'Yang Hu 0001' in GoogleThis author has not been identified. Look up 'Shouyi Yin' in Google

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