Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu 0001, Shouyi Yin. Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. In Vivek De, editor, Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024. ACM, 2024. [doi]
@inproceedings{XiangYLLW0Y24,
title = {Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization},
author = {Xujiang Xiang and Zhiheng Yue and Yuxuan Li and Liuxin Lv and Shaojun Wei and Yang Hu 0001 and Shouyi Yin},
year = {2024},
doi = {10.1145/3649329.3655690},
url = {https://doi.org/10.1145/3649329.3655690},
researchr = {https://researchr.org/publication/XiangYLLW0Y24},
cites = {0},
citedby = {0},
booktitle = {Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024},
editor = {Vivek De},
publisher = {ACM},
isbn = {979-8-4007-0601-1},
}