Xujiang Xiang, Zhiheng Yue, Xiaolong Zhang, Shaojun Wei, Yang Hu 0001, Shouyi Yin. Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. IEEE Trans. Circuits Syst. I Regul. Pap., 72(5):2216-2228, May 2025. [doi]
@article{XiangYZWHY25,
title = {Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization},
author = {Xujiang Xiang and Zhiheng Yue and Xiaolong Zhang and Shaojun Wei and Yang Hu 0001 and Shouyi Yin},
year = {2025},
month = {May},
doi = {10.1109/TCSI.2025.3547001},
url = {https://doi.org/10.1109/TCSI.2025.3547001},
researchr = {https://researchr.org/publication/XiangYZWHY25},
cites = {0},
citedby = {0},
journal = {IEEE Trans. Circuits Syst. I Regul. Pap.},
volume = {72},
number = {5},
pages = {2216-2228},
}