Xujiang Xiang, Zhiheng Yue, Xiaolong Zhang, Shaojun Wei, Yang Hu 0001, Shouyi Yin. Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. IEEE Trans. Circuits Syst. I Regul. Pap., 72(5):2216-2228, May 2025. [doi]
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