A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Zhibin Xiao, Bevan M. Baas. A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks. In Andreas Burg, Ayse Kivilcim Coskun, Matthew R. Guthaus, Srinivas Katkoori, Ricardo Reis, editors, VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers. Volume 418 of IFIP Advances in Information and Communication Technology, pages 125-143, Springer, 2012. [doi]

Authors

Zhibin Xiao

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Bevan M. Baas

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