VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers - researchr publication

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Andreas Burg, Ayse Kivilcim Coskun, Matthew R. Guthaus, Srinivas Katkoori, Ricardo Reis, editors, VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers. Volume 418 of IFIP Advances in Information and Communication Technology, Springer, 2013. [doi]

Conference: vlsi2013

Abstract is missing.

FPGA-Based High-Speed Authenticated Encryption SystemMichael Muehlberghuber, Christoph Keller, Frank K. Gürkaynak, Norbert Felber. 1-20 [doi]

A Smart Memory Accelerated Computed Tomography Parallel BackprojectionQiuling Zhu, Larry Pileggi, Franz Franchetti. 21-44 [doi]

Trinocular Stereo Vision Using a Multi Level Hierarchical Classification StructureAndy Motten, Luc Claesen, Yun Pan. 45-63 [doi]

Spatially-Varying Image Warping: Evaluations and VLSI ImplementationsPierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gürkaynak, Aljoscha Smolic. 64-87 [doi]

An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed SensingJeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg. 88-106 [doi]

Configurable Low-Latency Interconnect for Multi-core ClustersGiulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini. 107-124 [doi]

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip NetworksZhibin Xiao, Bevan M. Baas. 125-143 [doi]

Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip InterconnectionsAnelise Kologeski, Caroline Concatto, Fernanda Lima Kastensmidt, Luigi Carro. 144-161 [doi]

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW ProcessorsDavide Sabena, Luca Sterpone, Matteo Sonza Reorda. 162-180 [doi]

SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array ArchitectureSeokjoong Kim, Matthew R. Guthaus. 181-195 [doi]

CMOS Implementation of Threshold Gates with HysteresisFarhad Alibeygi Parsan, Scott C. Smith. 196-216 [doi]

Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-GatesNeil Di Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra, Paul D. Franzon. 217-233 [doi]

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