The following publications are possibly variants of this publication:
- Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise ChannelsWeihuang Wang, Euncheol Kim, Kiran K. Gunnam, Gwan S. Choi. jolpe, 5(3):303-312, 2009. [doi]
- Low Power Design of Asynchronous Datapath for LDPC DecoderXiaobo Jiang, DeSheng Ye, Hongyuan Li, Wentao Wu, Xiangmin Xu. ieicet, 96-A(9):1857-1863, 2013. [doi]
- Quantized LDPC decoder design for binary symmetric channelsRohit Singhal, Gwan S. Choi, Rabi N. Mahapatra. iscas 2005: 5782-5785 [doi]