A Low-Latency Hardware Architecture Design for Five-Error-Correcting Reed-Solomon Decoder

Haobin Xu, Zichuan Qiu, Suwen Song, Zhongfeng Wang 0001, Liyang Zhou. A Low-Latency Hardware Architecture Design for Five-Error-Correcting Reed-Solomon Decoder. IEEE Trans. VLSI Syst., 34(7):2321-2325, July 2026. [doi]

Abstract

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