Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture - researchr publication related

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Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha. Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture. In 12th International Conference on Parallel and Distributed Systems (ICPADS 2006), 12-15 July 2006, Minneapolis, Minnesota, USA. pages 375-382, IEEE Computer Society, 2006. [doi]

The following publications are possibly variants of this publication:

Iterational retiming with partitioning: Loop scheduling with complete memory latency hidingChun Jason Xue, Jingtong Hu, Zili Shao, Edwin Hsing-Mean Sha. tecs, 9(3), 2010. [doi]

Loop Scheduling and Partitions for Hiding Memory LatenciesFei Chen, Edwin Hsing-Mean Sha. isss 1999: 64-70 [doi]

High Performance Memory Management for a Multi-core ArchitectureMengxiao Liu, Weixing Ji, Zuo Wang, Jiaxin Li, Xing Pu. IEEEcit 2009: 63-68 [doi]

Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memoryMeikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha. fpl 2008: 459-462 [doi]

Optimal Loop Tiling for Minimizing Write Operations on NVMs with Complete Memory Latency HidingRui Xu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Yuhong Song, Jingzhi Lin. aspdac 2022: 389-394 [doi]

Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applicationsZhong Wang, Michael Kirkpatrick, Edwin Hsing-Mean Sha. dac 2000: 540-545 [doi]

Optimal loop scheduling for hiding memory latency based on two-level partitioning and prefetchingZhong Wang, Timothy W. O'Neil, Edwin Hsing-Mean Sha. tsp, 49(11):2853-2864, 2001. [doi]

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