A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme - researchr publication authors

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Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada. A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. In Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan. pages 3-4, ACM, 2001. [doi]

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