Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada. A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. In Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan. pages 3-4, ACM, 2001. [doi]
@inproceedings{YamaokaIA01,
title = {A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme},
author = {Hiroaki Yamaoka and Makoto Ikeda and Kunihiro Asada},
year = {2001},
doi = {10.1145/370155.370195},
url = {http://doi.acm.org/10.1145/370155.370195},
tags = {logic},
researchr = {https://researchr.org/publication/YamaokaIA01},
cites = {0},
citedby = {0},
pages = {3-4},
booktitle = {Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
publisher = {ACM},
isbn = {0-7803-6634-4},
}