A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design

Masanao Yamaoka, Hidetoshi Onodera. A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design. In 2006 IEEE International SOC Conference, Austin, Texas, USA, September 24-27, 2006. pages 315-318, IEEE, 2006. [doi]

Authors

Masanao Yamaoka

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Hidetoshi Onodera

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