Masanao Yamaoka, Hidetoshi Onodera. A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design. In 2006 IEEE International SOC Conference, Austin, Texas, USA, September 24-27, 2006. pages 315-318, IEEE, 2006. [doi]
@inproceedings{YamaokaO06,
title = {A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design},
author = {Masanao Yamaoka and Hidetoshi Onodera},
year = {2006},
doi = {10.1109/SOCC.2006.283905},
url = {http://dx.doi.org/10.1109/SOCC.2006.283905},
researchr = {https://researchr.org/publication/YamaokaO06},
cites = {0},
citedby = {0},
pages = {315-318},
booktitle = {2006 IEEE International SOC Conference, Austin, Texas, USA, September 24-27, 2006},
publisher = {IEEE},
isbn = {0-7803-9781-9},
}