Hideo Yamasaki, Tadashi Shibata. A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits. In Laurent Fesquet, Andreas Kaiser, Sorin Cristoloveanu, Michel Brillouët, editors, Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005. pages 125-128, IEEE, 2005. [doi]
@inproceedings{YamasakiS05a,
title = {A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits},
author = {Hideo Yamasaki and Tadashi Shibata},
year = {2005},
doi = {10.1109/ESSCIR.2005.1541575},
url = {https://doi.org/10.1109/ESSCIR.2005.1541575},
researchr = {https://researchr.org/publication/YamasakiS05a},
cites = {0},
citedby = {0},
pages = {125-128},
booktitle = {Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005},
editor = {Laurent Fesquet and Andreas Kaiser and Sorin Cristoloveanu and Michel Brillouët},
publisher = {IEEE},
isbn = {0-7803-9205-1},
}