Hideo Yamasaki, Tadashi Shibata. A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits. In Laurent Fesquet, Andreas Kaiser, Sorin Cristoloveanu, Michel Brillouët, editors, Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005. pages 125-128, IEEE, 2005. [doi]
Abstract is missing.