A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses

Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami. A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. IEICE Transactions, 90-C(4):749-757, 2007. [doi]

Abstract

Abstract is missing.