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Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami. A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. IEICE Transactions, 90-C(4):749-757, 2007. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed AccessesToshikazu Suzuki, Hiroyuki Yamauchi, Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu. jssc, 43(9):2109-2119, 2008. [doi]
The following publications are possibly variants of this publication: