Jin-Tai Yan, Bo-Yi Chiang. Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. pages 899-906, IEEE Computer Society, 2007. [doi]
Abstract is missing.