Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Zhichao Yan, Hong Jiang 0001, Witawas Srisa-an, Sharad C. Seth, Yujuan Tan. Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability. In Proceedings of the 47th International Conference on Parallel Processing, ICPP 2018, Eugene, OR, USA, August 13-16, 2018. ACM, 2018. [doi]

This author has not been identified. Look up 'Zhichao Yan' in GoogleThis author has not been identified. Look up 'Hong Jiang 0001' in GoogleThis author has not been identified. Look up 'Witawas Srisa-an' in GoogleThis author has not been identified. Look up 'Sharad C. Seth' in GoogleThis author has not been identified. Look up 'Yujuan Tan' in Google

runs on WebDSL