Zhichao Yan, Hong Jiang 0001, Witawas Srisa-an, Sharad C. Seth, Yujuan Tan. Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability. In Proceedings of the 47th International Conference on Parallel Processing, ICPP 2018, Eugene, OR, USA, August 13-16, 2018. ACM, 2018. [doi]
Abstract is missing.