Zhichao Yan, Hong Jiang 0001, Witawas Srisa-an, Sharad C. Seth, Yujuan Tan. Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability. In Proceedings of the 47th International Conference on Parallel Processing, ICPP 2018, Eugene, OR, USA, August 13-16, 2018. ACM, 2018. [doi]
@inproceedings{YanJSST18,
title = {Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability},
author = {Zhichao Yan and Hong Jiang 0001 and Witawas Srisa-an and Sharad C. Seth and Yujuan Tan},
year = {2018},
doi = {10.1145/3225058.3225093},
url = {https://doi.org/10.1145/3225058.3225093},
researchr = {https://researchr.org/publication/YanJSST18},
cites = {0},
citedby = {0},
booktitle = {Proceedings of the 47th International Conference on Parallel Processing, ICPP 2018, Eugene, OR, USA, August 13-16, 2018},
publisher = {ACM},
}