Jin-Tai Yan, Chia-Fang Lee, Tzu-Ya Wang. Floorplan-aware Steiner tree reconstruction for optimal buffer insertion. In 12th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2005, Gammarth, Tunisia, December 11-14, 2005. pages 1-4, IEEE, 2005. [doi]
Abstract is missing.