Yang Yang, Niraj K. Jha. Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations. In 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. pages 350-355, IEEE, 2013. [doi]
@inproceedings{YangJ13-0,
title = {Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations},
author = {Yang Yang and Niraj K. Jha},
year = {2013},
doi = {10.1109/VLSID.2013.213},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2013.213},
researchr = {https://researchr.org/publication/YangJ13-0},
cites = {0},
citedby = {0},
pages = {350-355},
booktitle = {26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4639-9},
}