Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations - researchr publication

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Yang Yang, Niraj K. Jha. Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations. In 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. pages 350-355, IEEE, 2013. [doi]

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