A 10-bit 50-MS/s SAR ADC employing PN-assisted LMS calibration and robust register logic achieving 78.4-dB SFDR - researchr publication authors

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Xijun Yang, Siqi Men, Yuzhuan Shi, Jie Sun. A 10-bit 50-MS/s SAR ADC employing PN-assisted LMS calibration and robust register logic achieving 78.4-dB SFDR. Microelectronics Journal, 174:107200, 2026. [doi]

This author has not been identified. Look up 'Xijun Yang' in GoogleThis author has not been identified. Look up 'Siqi Men' in GoogleThis author has not been identified. Look up 'Yuzhuan Shi' in GoogleThis author has not been identified. Look up 'Jie Sun' in Google

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