A 10-bit 50-MS/s SAR ADC employing PN-assisted LMS calibration and robust register logic achieving 78.4-dB SFDR

Xijun Yang, Siqi Men, Yuzhuan Shi, Jie Sun. A 10-bit 50-MS/s SAR ADC employing PN-assisted LMS calibration and robust register logic achieving 78.4-dB SFDR. Microelectronics Journal, 174:107200, 2026. [doi]

Abstract

Abstract is missing.