Xinghua Yang, Fei Qiao, Chang Liu, Qi Wei, Huazhong Yang. Design of multi-stage latency adders using detection and sequence-dependence between successive calculations. In IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014. pages 998-1001, IEEE, 2014. [doi]
Abstract is missing.