A clock-gating based capture power droop reduction methodology for at-speed scan testing - researchr publication authors

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Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu. A clock-gating based capture power droop reduction methodology for at-speed scan testing. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011. pages 197-203, IEEE, 2011. [doi]

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