Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu. A clock-gating based capture power droop reduction methodology for at-speed scan testing. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011. pages 197-203, IEEE, 2011. [doi]
@inproceedings{YangSSL11,
title = {A clock-gating based capture power droop reduction methodology for at-speed scan testing},
author = {Bo Yang and Amit Sanghani and Shantanu Sarangi and Chunsheng Liu},
year = {2011},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5763042},
researchr = {https://researchr.org/publication/YangSSL11},
cites = {0},
citedby = {0},
pages = {197-203},
booktitle = {Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011},
publisher = {IEEE},
isbn = {978-1-61284-208-0},
}