Secure Scan: A Design-for-Test Architecture for Crypto Chips

Bo Yang, Kaijie Wu, Ramesh Karri. Secure Scan: A Design-for-Test Architecture for Crypto Chips. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(10):2287-2293, 2006. [doi]

@article{YangWK06:2,
  title = {Secure Scan: A Design-for-Test Architecture for Crypto Chips},
  author = {Bo Yang and Kaijie Wu and Ramesh Karri},
  year = {2006},
  doi = {10.1109/TCAD.2005.862745},
  url = {http://doi.ieeecomputersociety.org/10.1109/TCAD.2005.862745},
  tags = {architecture, testing, design},
  researchr = {https://researchr.org/publication/YangWK06%3A2},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {25},
  number = {10},
  pages = {2287-2293},
}