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Peilin Yang, Xiao Wang 0021, Chengwei Wang, Fule Li, Hanjun Jiang, Zhihua Wang 0001. A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction. IEEE Trans. VLSI Syst., 28(9):2004-2013, 2020. [doi]
Abstract is missing.