Tree-model based mapping for energy-efficient and low-latency Network-on-Chip - researchr publication authors

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Bo Yang 0009, Thomas Canhao Xu, Tero Säntti, Juha Plosila. Tree-model based mapping for energy-efficient and low-latency Network-on-Chip. In Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann, editors, 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010. pages 189-192, IEEE, 2010. [doi]

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