Tree-model based mapping for energy-efficient and low-latency Network-on-Chip

Bo Yang 0009, Thomas Canhao Xu, Tero Säntti, Juha Plosila. Tree-model based mapping for energy-efficient and low-latency Network-on-Chip. In Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann, editors, 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010. pages 189-192, IEEE, 2010. [doi]

@inproceedings{YangXSP10,
  title = {Tree-model based mapping for energy-efficient and low-latency Network-on-Chip},
  author = {Bo Yang 0009 and Thomas Canhao Xu and Tero Säntti and Juha Plosila},
  year = {2010},
  doi = {10.1109/DDECS.2010.5491789},
  url = {http://doi.ieeecomputersociety.org/10.1109/DDECS.2010.5491789},
  researchr = {https://researchr.org/publication/YangXSP10},
  cites = {0},
  citedby = {0},
  pages = {189-192},
  booktitle = {13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010},
  editor = {Elena Gramatová and Zdenek Kotásek and Andreas Steininger and Heinrich Theodor Vierhaus and Horst Zimmermann},
  publisher = {IEEE},
  isbn = {978-1-4244-6612-2},
}