Jheng-Hao Ye, Ming-Der Shieh. High-performance NTT architecture for large integer multiplication. In 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018. pages 1-4, IEEE, 2018. [doi]
@inproceedings{YeS18,
title = {High-performance NTT architecture for large integer multiplication},
author = {Jheng-Hao Ye and Ming-Der Shieh},
year = {2018},
doi = {10.1109/VLSI-DAT.2018.8373254},
url = {https://doi.org/10.1109/VLSI-DAT.2018.8373254},
researchr = {https://researchr.org/publication/YeS18},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018},
publisher = {IEEE},
isbn = {978-1-5386-4260-3},
}