A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity

Dawei Ye, Rongjin Xu, C.-J. Richard Shi. A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity. In IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019. pages 414-416, IEEE, 2019. [doi]

@inproceedings{YeXS19,
  title = {A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity},
  author = {Dawei Ye and Rongjin Xu and C.-J. Richard Shi},
  year = {2019},
  doi = {10.1109/ISSCC.2019.8662451},
  url = {https://doi.org/10.1109/ISSCC.2019.8662451},
  researchr = {https://researchr.org/publication/YeXS19},
  cites = {0},
  citedby = {0},
  pages = {414-416},
  booktitle = {IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019},
  publisher = {IEEE},
  isbn = {978-1-5386-8531-0},
}