David Yeh, Gennady Feygin, Paul Chow. RACER: a reconfigurable constraint-length 14 Viterbi decoder. In 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), Napa Valley, CA, USA, April 17-19, 1996. pages 60-69, IEEE, 1996. [doi]
@inproceedings{YehFC96,
title = {RACER: a reconfigurable constraint-length 14 Viterbi decoder},
author = {David Yeh and Gennady Feygin and Paul Chow},
year = {1996},
doi = {10.1109/FPGA.1996.564746},
url = {http://dx.doi.org/10.1109/FPGA.1996.564746},
researchr = {https://researchr.org/publication/YehFC96},
cites = {0},
citedby = {0},
pages = {60-69},
booktitle = {4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), Napa Valley, CA, USA, April 17-19, 1996},
publisher = {IEEE},
isbn = {0-8186-7548-9},
}