RACER: a reconfigurable constraint-length 14 Viterbi decoder

David Yeh, Gennady Feygin, Paul Chow. RACER: a reconfigurable constraint-length 14 Viterbi decoder. In 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), Napa Valley, CA, USA, April 17-19, 1996. pages 60-69, IEEE, 1996. [doi]

Abstract

Abstract is missing.