Kumar Yelamarthi, Chien-In Henry Chen. Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. In 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA. pages 426-431, IEEE Computer Society, 2007. [doi]
Abstract is missing.