The following publications are possibly variants of this publication:
- Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing OptimizationKumar Yelamarthi, Chien-In Henry Chen. jcp, 3(2):21-28, 2008. [doi]
- Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process VariationsKumar Yelamarthi, Chien-In Henry Chen. vlsi, 2010, 2010. [doi]
- Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS LogicKumar Yelamarthi, Chien-In Henry Chen. isqed 2008: 143-147 [doi]
- Delay optimization considering power saving in dynamic CMOS circuitsKumar Yelamarthi, Chien-In Henry Chen. isqed 2011: 364-369 [doi]
- Timing and Power Optimization by Gate Sizing Considering False PathsGuangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru. glvlsi 1996: 154 [doi]