Abstract is missing.
- Analysis and mitigation of NBTI aging in register file: An end-to-end approachSaurabh Kothawade, Koushik Chakraborty, Sanghamitra Roy. 1-7 [doi]
- Reducing impact of degradation on analog circuits by chopper stabilization and autozeroingShailesh More, Michael Fulde, Florian Chouard, Doris Schmitt-Landsiedel. 8-13 [doi]
- Circuit-level delay modeling considering both TDDB and NBTIHong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang. 14-21 [doi]
- Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuationKyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera. 22-27 [doi]
- Modeling and analyzing NBTI in the presence of Process VariationTaniya Siddiqua, Sudhanva Gurumurthi, Mircea R. Stan. 28-35 [doi]
- A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuitsQiang Gao, Hailong Yao, Qiang Zhou, Yici Cai. 36-41 [doi]
- Signal integrity analysis and optimization for 3D ICsChang Liu, Taigon Song, Sung Kyu Lim. 42-49 [doi]
- 3DICE: 3D IC cost evaluation based on fast tier number estimationCheng-Chi Chan, Yen-Ting Yu, Iris Hui-Ru Jiang. 50-55 [doi]
- Accurate analysis of substrate sensitivity of active transistors in an analog circuitSatoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata. 56-61 [doi]
- Full-chip analysis of unintentional forward biased diodesAmir Grinshpon, Adam Segoli Schubert, Ziyang Lu. 62-66 [doi]
- A 12.4μm:::2::: 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operationBasab Datta, Wayne Burleson. 67-73 [doi]
- Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneouslyLi Li, Ken Choi, Haiqing Nan. 74-79 [doi]
- Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnectsKyu-Nam Shim, Jiang Hu. 80-86 [doi]
- A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiersMichael Wieckowski, Gregory K. Chen, Daeyeon Kim, David Blaauw, Dennis Sylvester. 87-90 [doi]
- Temperature aware energy management for real-time schedulingNikhil Gupta, Rabi N. Mahapatra. 91-96 [doi]
- Coupling timing objectives with optical proximity correction for improved timing yieldShayak Banerjee, Kanak B. Agarwal, Sani R. Nassif, James A. Culp, Lars Liebmann, Michael Orshansky. 97-102 [doi]
- Self-aligned double patterning (SADP) layout decompositionMinoo Mirsaeedi, J. Andres Torres, Mohab Anis. 103-109 [doi]
- DFM: Impact analysis in a high performance designS. M. Stalin, Amit Brahme, Venkatraman Ramakrishnan, Ajoy Mandal. 110-115 [doi]
- Metrics for characterizing machine learning-based hotspot detection methodsJen-Yi Wuu, Fedor G. Pikus, Malgorzata Marek-Sadowska. 116-121 [doi]
- Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICsTaigon Song, Chang Liu, Dae-Hyun Kim, Sung Kyu Lim, Jonghyun Cho, Joohee Kim, Junso Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon. 122-128 [doi]
- 3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvementDing-Ming Kwai, Chang-Tzu Lin. 129-134 [doi]
- Virtual Hellfire Hypervisor: Extending Hellfire Framework for embedded virtualization supportAlexandra Aguiar, Fabiano Hessel. 129-203 [doi]
- Compact circuit modeling of RF characteristics of 1-D nanostructuresCary Y. Yang. 135 [doi]
- SCPlace: A statistical slack-assignment based constructive placerEvriklis Kounalakis, Christos P. Sotiriou. 136-143 [doi]
- Application-specific Network-on-Chip synthesis: Cluster generation and network component insertionWei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto. 144-149 [doi]
- Novel and efficient min cut based voltage assignment in gate levelTao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto. 150-155 [doi]
- Multi-objective optimization techniques for VLSI circuitsFatemeh Kashfi, Safar Hatami, Massoud Pedram. 156-163 [doi]
- A design time simulator for computer architectsSangeetha Sudhakrishnan, Francisco J. Mesa-Martinez, Jose Renau. 164-173 [doi]
- Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimizationChia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao, Sy-Yen Kuo. 174-181 [doi]
- POSEIDON: A framework for application-specific Network-on-Chip synthesis for heterogeneous chip multiprocessorsSoohyun Kwon, Sudeep Pasricha, Jeonghun Cho. 182-188 [doi]
- A complete framework of simultaneous functional unit and register binding with skew schedulingMineo Kaneko. 189-195 [doi]
- A low overhead fault tolerant routing scheme for 3D Networks-on-ChipSudeep Pasricha, Yong Zou. 204-211 [doi]
- Integrated circuit-architectural framework for PSN aware floorplanning in microprocessorsMandar Padmawar, Sanghamitra Roy, Koushik Chakraborty. 212-218 [doi]
- 0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAMHiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi. 219-222 [doi]
- Power-supply-network design in 3D integrated systemsMichael B. Healy, Sung Kyu Lim. 223-228 [doi]
- An automated design methodology for yield aware analog circuit synthesis in submicron technologySabyasachi Deyati, Pradip Mandal. 229-235 [doi]
- Process variation sensitivity of the Rotary Traveling Wave OscillatorYing Teng, Baris Taskin. 236-242 [doi]
- Enhancement of incremental design for FPGAs using circuit similarityXiaoyu Shi, Dahua Zeng, Yu Hu, Guohui Lin, Osmar R. ZaĂ¯ane. 243-250 [doi]
- On discovery of missing physical design rules via diagnosis of soft-faultsAswin Sreedhar, Sandip Kundu. 251-256 [doi]
- Mixed non-rectangular block packing for non-Manhattan layout architecturesMeng-Chen Wu, Hung-Ming Chen, Jing-Yang Jou. 257-262 [doi]
- Optimizing simulated annealing on GPU: A case study with IC floorplanningYiding Han, Sanghamitra Roy, Koushik Chakraborty. 263-269 [doi]
- Floorplanning for high utilization of heterogeneous FPGAsNan Liu, Song Chen, Takeshi Yoshimura. 270-275 [doi]
- Efficient directed test generation for validation of multicore architecturesXiaoke Qin, Prabhat Mishra. 276-283 [doi]
- Global transaction ordering in Network-on-Chips for post-silicon validationAmir Masoud Gharehbaghi, Masahiro Fujita. 284-289 [doi]
- On evaluating signal selection algorithms for post-silicon debugEddie Hung, Steven J. E. Wilton. 290-296 [doi]
- Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniquesBijan Alizadeh, Masahiro Fujita. 297-302 [doi]
- RF BIST for ADPLL-based polar transmitters with wide-band DCO gain calibrationLeyi Yin, Peng Li. 303-310 [doi]
- CMP monitoring and prediction based metal fillPhilippe Morey-Chaisemartin, Eric Beisser, Jean-Claude Marin, Lidwine Chaize, Pascal Guyader, Julien Rosa. 311-416 [doi]
- A 90 nm low-power successive approximation register for A/D conversionsMohamed O. Shaker, Magdy A. Bayoumi. 311-315 [doi]
- A low noise CMOS interface circuit for capacitive liquid crystal chemical and biological sensorAlireza Hassanzadeh, Robert G. Lindquist. 316-321 [doi]
- Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal controlMasahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto. 322-325 [doi]
- pH sensing with temperature compensation in a Molecular Biosensor for drugs detectionDaniela De Venuto, Sandro Carrara, Andrea Cavallini, Giovanni De Micheli. 326-331 [doi]
- CMOS diodes operating beyond avalanche frequencyTalal Al-Attar. 332-337 [doi]
- Entropy-reduced hashing for physical IP managementSandeep Koranne, John Ferguson, Bikram Garg, Manish Khanna. 338-342 [doi]
- A physical model for tunable patch antennasBenjamin D. Horwath, Talal Al-Attar. 343-346 [doi]
- Model analysis of multi-finger MOSFET layout in ring oscillator designBo Jiang, Tian Xia. 347-352 [doi]
- Crosstalk aware coupled line delay tree construction for on-chip interconnectsTuhina Samanta, Sanoara Khatun, Hafizur Rahaman, Parthasarathi Dasgupta. 353-358 [doi]
- A layer prediction method for minimum cost three dimensional integrated circuitsTsu-Yun Hsueh, Hsiang-Hui Yang, Wei-Chieh Wu, Mely Chen Chi. 359-363 [doi]
- Delay optimization considering power saving in dynamic CMOS circuitsKumar Yelamarthi, Chien-In Henry Chen. 364-369 [doi]
- Capacitor free phase locked loop design in 45nmAnisha Raj Seli, Hoa Nguyen, Lili He 0001, Morris Jones. 370-375 [doi]
- Model based double patterning lithography (DPL) and simulated annealing (SA)Rance Rodrigues, Sandip Kundu. 376-383 [doi]
- Comparative BTI reliability analysis of SRAM cell designs in nano-scale CMOS technologyShreyas Kumar Krishnappa, Hamid Mahmoodi. 384-389 [doi]
- Design method of NOR-type comparison circuit in CAM with ground bounce noise considerationsChangmin Jung, Sanghyeon Baeg, Shihie Wen, Richard Wong. 390-397 [doi]
- A 12-bit CMOS current steering D/A converter with a fully differential voltage outputGuoyuan Fu, H. Alan Mantooth, Jia Di. 398-404 [doi]
- Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodelingOleg Garitselov, Saraju P. Mohanty, Elias Kougianos. 405-410 [doi]
- Non-Gaussian uncertainty propagation in statistical circuit simulationQian Ying Tang, Costas J. Spanos. 417-424 [doi]
- New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nmRandy W. Mann, Benton H. Calhoun. 425-430 [doi]
- A sensitivity-aware methodology to improve cell layouts for DFM guidelinesSavithri Sundareswaran, Robert L. Maziasz, Vladimir Rozenfeld, Mikhail Sotnikov, Mukhanov Konstantin. 431-436 [doi]
- Lithography-aware layout modification considering performance impactHongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao. 437-441 [doi]
- Tracking hardware evolutionJosĂ© Augusto Miranda Nacif, Thiago S. F. Silva, Luiz Filipe M. Vieira, Alex Borges Vieira, AntĂ´nio OtĂ¡vio Fernandes, Claudionor Coelho. 442-447 [doi]
- An accurate and scalable MOSFET aging model for circuit simulationBogdan Tudor, Joddy Wang, Zhaoping Chen, Robin Tan, Weidong Liu, Frank Lee. 448-451 [doi]
- Fast variational static IR-drop analysis on the graphical processing unitRasit Onur Topaloglu. 452-457 [doi]
- Efficient nanoscale VLSI standard cell library characterization using a novel delay modelSandeep Miryala, Baljit Kaur, Bulusu Anand, Sanjeev Manhas. 458-463 [doi]
- Occurrence probability analysis of a path at the architectural levelDheepakkumaran Jayaraman, Spyros Tragoudas. 464-468 [doi]
- Automatic post-layout flow validation tool for Deep Sub-micron process design kitsPinping Sun, Cole Zemke, Wayne H. Woods, Nick Perez, Hailing Wang, Essam Mina, Barbara Dewitt. 469-472 [doi]
- Switching constraint-driven thermal and reliability analysis of Nanometer designsSrini Krishnamoorthy, Vishak Venkatraman, Yuri Apanovich, Thomas Burd, Anand Daga. 473-480 [doi]
- Separation of communication and computation in SystemC/TLM modeling: A Feature-Oriented approachJun Ye, Qingping Tan, Tun Li. 481-485 [doi]
- Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space explorationAnirban Sengupta, Reza Sedaghat. 486-494 [doi]
- Exploring performance-power tradeoffs in providing reliability for NoC-based MPSoCsHui Zhao, Mahmut T. Kandemir, Mary Jane Irwin. 495-501 [doi]
- Stratus: Free design of highly parametrized VLSI modules interoperable with commercial toolsSophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez. 502-507 [doi]
- Variation-aware stochastic extraction with large parameter dimensionality: Review and comparison of state of the art intrusive and non-intrusive techniquesTarek A. El-Moselhy, Luca Daniel. 508-517 [doi]
- Digitally programmable SRAM timing for nano-scale technologiesAdam Neale, Manoj Sachdev. 518-524 [doi]
- Layout-aware mismatch modeling for CMOS current sources with D/A converter analysisBo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake. 525-532 [doi]
- Using NMOS transistors as switches for accuracy and area-efficiency in large-scale addressable test arrayWeiwei Pan, Jie Ren, Yongjun Zheng, Zheng Shi, Xiaolang Yan. 533-538 [doi]
- A simple array-based test structure for the AC variability characterization of MOSFETsKarthik Balakrishnan, Keith A. Jenkins, Duane S. Boning. 539-544 [doi]
- Reliability - A highly important product attribute for the world s poorest consumersJoseph Fjelstad. 545-547 [doi]
- Cost-effective optimization of serial link system for Signal Integrity and Power IntegrityRaj Kumar Nagpal, Jai Narayan Tripathi, Rakesh Malik. 548-552 [doi]
- Package-chip co-design to increase flip-chip C4 reliabilitySheldon Logan, Matthew R. Guthaus. 553-558 [doi]
- Maximizing hotspot temperature: Wavelet based modelling of heating and cooling profile of functional workloadsSudarshan Srinivasan, Kunal P. Ganeshpure, Sandip Kundu. 559-565 [doi]
- Process variation aware system-level load assignment for total energy minimization using stochastic orderingShahin Golshan, Love Singhal, Eli Bozorgzadeh. 566-571 [doi]
- A low cost approach to calibrate on-chip thermal sensorsKrishna Bharath, Chunhua Yao, Nam Sung Kim, Parameswaran Ramanathan, Kewal K. Saluja. 572-576 [doi]
- Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memoryKyungsu Kang, Jongpil Jung, Sungjoo Yoo, Chong-Min Kyung. 577-582 [doi]
- Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flopsDavid Li, David Rennie, Pierce Chuang, David Nairn, Manoj Sachdev. 583-590 [doi]
- ERAVC: Enhanced reliability aware NoC routerMohammad Hossein Neishaburi, Zeljko Zilic. 591-596 [doi]
- SEU tolerant SRAM cellSudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita. 597-602 [doi]
- Soft error reduction through gate input dependent weighted sizing in combinational circuitsWarin Sootkaneung, Kewal K. Saluja. 603-610 [doi]
- Low power latch design in near sub-threshold region to improve reliability for soft errorSandeep Sriram, Haiqing Nan, Ken Choi. 611-614 [doi]
- BCH code based multiple bit error correction in finite field multiplier circuitsMahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty. 615-620 [doi]
- A novel fine-grain track routing approach for routability and crosstalk optimizationZhongdong Qi, Qiang Zhou, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao. 621-626 [doi]
- Redundant via insertion under timing constraintsChi-Wen Pan, Yu-Min Lee. 627-633 [doi]
- A new ECO technology for functional changes and removing timing violationsJui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh. 634-638 [doi]
- The effect of SRNR on timing characteristics of signal bussesBassel Soudan. 639-645 [doi]
- Gridless wire ordering, sizing and spacing with critical area minimizationYu-Wei Lee, Yen-Hung Lin, Yih-Lang Li. 646-653 [doi]
- Clock planning for multi-voltage and multi-mode designsChang-Cheng Tsai, Tzu-Hen Lin, Shin-Han Tsai, Hung-Ming Chen. 654-658 [doi]
- Fast power delivery network analyzerBosun Hwang, Jongeun Koo, Chanseok Hwang, Younghoi Cheon, Sooyoung Ahn, Jongbae Lee, Moonhyun Yoo. 659-662 [doi]
- Efficient checking of power delivery integrity for power gatingZhiyu Zeng, Zhuo Feng, Peng Li. 663-670 [doi]
- An efficient statistical chip-level total power estimation method considering process variations with spatial correlationZhigang Hao, Sheldon X.-D. Tan, Guoyong Shi. 671-676 [doi]
- Statistical full-chip dynamic power estimation considering spatial correlationsZhigang Hao, Ruijing Shen, Sheldon X.-D. Tan, Bao Liu, Guoyong Shi, Yici Cai. 677-682 [doi]
- Stepped Supply Voltage Switching for energy constrained systemsSudhanshu Khanna, Kyle Craig, Yousef Shakhsheer, Saad Arrabi, John Lach, Benton H. Calhoun. 683-688 [doi]
- Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gatesKyungseok Kim, Vishwani D. Agrawal. 689-694 [doi]
- Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technologyAjay N. Bhoj, Niraj K. Jha. 695-702 [doi]
- Timing yield estimation of carbon nanotube-based digital circuits in the presence of nanotube density variation and metallic-nanotubesBehnam Ghavami, Mohsen Raji, Hossein Pedram. 703-710 [doi]
- Measuring within-die spatial variation profile through power supply current measurementsJim Plusquellic, Dhruva Acharyya, Kanak Agarwal. 711-715 [doi]
- Analysis of within-die process variation in 65nm FPGAsTim Tuan, Austin Lesea, Chris Kingsley, Steven Trimberger. 716-720 [doi]
- Estimating the probability density function of critical path delay via partial least squares dimension reductionYu Ben, Costas J. Spanos. 721-727 [doi]
- Complementary Nano-Electro-Mechanical Switch for ultra-low-power applications: Design and modelingKhawla Alzoubi, Daniel G. Saab, Sijing Han, Massood Tabib-Azar. 728-735 [doi]
- Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modelingShaloo Rakheja, Azad Naeemi. 736-744 [doi]
- Scaled LTPS TFTs for low-cost low-power applicationsSoo Youn Kim, Selin Baytok, Kaushik Roy. 745-750 [doi]
- Mitigating TSV-induced substrate noise in 3-D ICs using GND plugsNauman H. Khan, Syed M. Alam, Soha Hassoun. 751-756 [doi]
- Device and circuit implications of double-patterning - A designer s perspectiveRasit Onur Topaloglu. 757-760 [doi]
- Automatic generation of saturation constraints and performance expressions for geometric programming based analog circuit sizingSupriyo Maji, Samiran Dam, Pradip Mandal. 761-768 [doi]
- Constructive AIG optimization considering input weightsThiago Figueiro, Renato P. Ribas, AndrĂ© InĂ¡cio Reis. 769-776 [doi]
- Integrated hierarchical synthesis of analog/RF circuits with accurate performance mappingKuo-Hsuan Meng, Po-Cheng Pan, Hung-Ming Chen. 777-784 [doi]
- A fully pipelined implementation of Monte Carlo based SSTA on FPGAsHiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato. 785-790 [doi]
- Multi-mode redundancy removalStephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho. 791-799 [doi]