Kumar Yelamarthi, Chien-In Henry Chen. Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. JCP, 3(2):21-28, 2008. [doi]
@article{YelamarthiC08,
title = {Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization},
author = {Kumar Yelamarthi and Chien-In Henry Chen},
year = {2008},
url = {http://www.academypublisher.com/jcp/vol03/no02/jcp03022128.html},
tags = {optimization, context-aware},
researchr = {https://researchr.org/publication/YelamarthiC08},
cites = {0},
citedby = {0},
journal = {JCP},
volume = {3},
number = {2},
pages = {21-28},
}