Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization - researchr publication references

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Kumar Yelamarthi, Chien-In Henry Chen. Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. JCP, 3(2):21-28, 2008. [doi]

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