High-performance iterative BCH decoder architecture for 100 Gb/s optical communications

Jewong Yeon, Hanho Lee. High-performance iterative BCH decoder architecture for 100 Gb/s optical communications. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013. pages 1344-1347, IEEE, 2013. [doi]

@inproceedings{YeonL13,
  title = {High-performance iterative BCH decoder architecture for 100 Gb/s optical communications},
  author = {Jewong Yeon and Hanho Lee},
  year = {2013},
  doi = {10.1109/ISCAS.2013.6572103},
  url = {http://dx.doi.org/10.1109/ISCAS.2013.6572103},
  researchr = {https://researchr.org/publication/YeonL13},
  cites = {0},
  citedby = {0},
  pages = {1344-1347},
  booktitle = {2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013},
  publisher = {IEEE},
  isbn = {978-1-4673-5760-9},
}