Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing - researchr publication authors

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Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi. Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing. J. Solid-State Circuits, 58(7):2098-2108, 2023. [doi]

This author has not been identified. Look up 'Yoshisato Yokoyama' in GoogleThis author has not been identified. Look up 'Koji Nii' in GoogleThis author has not been identified. Look up 'Yuichiro Ishii' in GoogleThis author has not been identified. Look up 'Shinji Tanaka' in GoogleThis author has not been identified. Look up 'Kazutoshi Kobayashi' in Google

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